Hybrid Microprocessor


The Story of the Little Computer That Could!


Revised 1/2/06

The NMOS II Hybrid Microprocessor:
Fusing silicon, ceramic, and aluminum with rubber baby buggy bumpers

Little more than engineering moxie convinced HP’s Loveland engineers that they could design and fabricate a 16-bit microprocessor in 1972. It should have been a recipe for disaster. Take a handful of engineers who had never designed a microprocessor; mix in a batch of unproven IC-design rules with a raw, new, and untried IC-fabrication process; then fold in the bold aspiration to leapfrog every company in the entire semiconductor and calculator arenas with a blissful ignorance of the pitfalls that lay ahead. The result should have been an unmitigated disaster. But, instead of disaster, the Loveland engineers baked a processor that stood the test of time for a decade, which is a very long lifetime for a processor, even back then.

No one at HP had ever designed a microprocessor before, not even at the much vaunted HP Labs. To date, the largest chip designed at HP Loveland was Dave Maitland’s 4-kbit ROM, which had been fabricated in HP Loveland’s first NMOS process and had been used extensively in the second-generation HP 9810A, 9820A, and 9830A desktop calculators.

In fact, almost no one in the world had designed a microprocessor in 1972. No one had yet designed a 16-bit microprocessor or any sort of microprocessor fabricated in NMOS. Intel introduced the world’s first commercial microprocessor, the 2300-transistor, 740-kHz (0.74 MHz), 4-bit 4004 microprocessor just a few months before—on November 15, 1971—and rolled out the follow-on, simultaneously developed, 3500-transistor, 800-kHz (0.8 MHz), 8-bit 8008 microprocessor in April, 1972. Both processors were designed for and fabricated with Intel’s PMOS IC process technology.

Microprocessors looked like a good technology bet even as early as 1972. The Loveland Calculator Division engineers and management at HP knew that the only way to stay well ahead of the calculator competition—primarily Wang at that time—was to make huge technological leaps that propelled HP’s capabilities far ahead of the other calculator vendors. Big advances are made by placing bets on tough development projects with stretch goals that produce the needed technological leaps. Development of HP’s in-house NMOS II IC-fabrication process was the first such leap. Using that NMOS process to create a world-beating, 16-bit, 10-MHz, NMOS microprocessor would be the second.

First step: Pick an Architecture

Bill Eads 1978 Small02

Bill Eads
Photo Courtesy Hewlett-Packard Company


Ed Olander 1967 small02

Ed Olander
Photo Courtesy Hewlett-Packard Company

Bill Eads joined HP’s Santa Clara Division in 1970. He had fabricated the IC photomasks for Dave Maitland’s NMOS I ROMs that went into HP’s second-generation desktop computers. He also developed some automated mask-layout tools that sped the ROM-development process. By 1972, Eads decided to move to Colorado for personal reasons. He transferred to the Calculator Division in Loveland in April, 1972 where he joined Ed Olander’s NMOS II processor-development team as its first team member. Olander had managed the development of the proto-HPL language code for the HP 9820A desktop calculator and he subsequently became the project manager for the NMOS II hybrid microprocessor development project. In those days, switching between hardware design, IC process development, and software development from project to project wasn’t unusual at HP. Well-rounded engineers were expected to be jacks of all trades, and masters at all of them too.

At first, the choice of processor architecture was initially left open. However, it didn’t take long for the processor team to zero in on HP’s 211x minicomputer architecture. Many aspects of this architecture made it the right choice but two stand out.

First, it was the processor architecture used in the second-generation desktop calculators so the experienced software developers in Loveland were already familiar with the HP 211x programmer’s model. Second, HP introduced the HP 2116A minicomputer in 1966 so the HP 211x architecture was already six years old by 1972 and there was substantial software-development support for the architecture (compilers, assembler, linker, loader, debugger, etc.). There was also an existing development platform—the HP 211x minicomputer family. (Today, we call these available tools the architecture’s “ecosystem” but microprocessor marketing wasn’t that sophisticated back then.) 

According to Maitland, the availability of HP 211x software-development tools finally forced the issue and the choice as made. HP Loveland would again use HP’s minicomputer architecture as the base for its third-generation calculator processor.

No call, no return

Some portions of the HP 211x architecture had to change to make it suitable for use as a desktop-calculator processor. Because almost all of the object code for the third-generation desktop calculators would run out of ROM, the HP 211x subroutine-call instruction had to be changed. The minicomputer version of this instruction stored the return address in the first location pointed to by the call instruction—a mechanism that worked fine for minicomputers, which used core-based read/write memory for program storage. For desktop calculators, the target location for the call instruction would likely be a ROM address and it would be impossible to store a return address in that location—after all, ROM stands for read-ONLY memory. Instead, a return stack was added to the new processor’s architecture to provide a set of RAM locations to store subroutine return addresses.

Dave Maitland02

Dave Maitland
Photo Courtesy Hewlett-Packard Company

In addition, the HP minicomputer’s I/O structure was deemed completely unsuitable for desktop computers. (“It was terrible,” says Maitland.) This isn’t a very surprising conclusion because the same conclusion had been made for the previous generation of desktop machines. So, once again, the minicomputer’s I/O instructions were “reinterpreted” to suit the desktop calculators’ needs. The revised architecture’s I/O structure also added a multi-level, hardware-vectored interrupt structure and direct-memory access (DMA), which vastly improved the hybrid microprocessor’s I/O abilities.

Another feature of the HP 211x minicomputer architecture that was removed was multi-level indirection. In the HP 211x minicomputer architecture, the uppermost bit of a memory-reference instruction (the 16th bit) serves as an indirect-bit indicator. If this bit is set, then the contents of the referenced location is used as an address pointing to the location of the target address for the memory-reference instruction. If the 16th bit of the value stored at that target address is set, that address is also an indirect pointer, and the processor uses the pointer to fetch the contents of the next location in the indirect chain. Eventually, the processor finds the actual desired value.

The HP 211x minicomputer’s ability to perform multiple-level indirection imposed a high cost—it reduced the processor’s addressable memory space by half, to 32 kwords (64 kbytes). That didn’t seem like much of a limitation when the HP 2116 was introduced in 1966 because back then, minicomputers all used very expensive and therefore very small read/write core memories. But it certainly would pinch the desktop calculator systems being designed in 1972. Eads looked at the operating system code written for the HP 211x minicomputers (RTE, the real-time executive) and found very few places where multi-level indirection was actually used. The feature was deleted from the hybrid microprocessor’s architecture.

Deleting the multi-level indirection feature gave the hybrid microprocessor full 64-kword (128-kbyte) addressing. Even 64 kwords of memory eventually proved inadequate for the growing amount of software in HP’s desktop machines and a block-switching chip would be added to the hybrid microprocessor to further enlarge the addressable memory space for the HP 9845A desktop computer.

Tom Osborne and ASM design

With the architecture chosen, attention turned to the implementation, the microarchitecture of the machine. No one on the team had ever built a microprocessor, so the project was treated as more of an exercise in logic design. Nearly 10 years earlier at the University of California at Berkeley, Tom Osborne had developed a comprehensive technique for designing state machines that he called “Algorithmic State Machine” (ASM) design. In 1965, he had used ASM design to create the prototype calculator that evolved into HP’s first-generation desktop calculator, the HP 9100, which was introduced in 1969.

Over the years, HP had fully embraced Osborne’s ASM design methodology. Chris Clare, a project manager in the Electronics Research Laboratory of HP Labs, started to organize and teach classes in ASM design attended by HP engineers from around the company. Clare would publish a book on ASM design in 1973 titled Designing Logic Systems Using State Machines. Tom Osborne had believed that his ASM design techniques would allow him to design anything. That same confidence infused the HP engineers in Loveland who faced the task of designing HP’s first microprocessor in 1972.

Chris Clare
Clare's Book 197302

Chris Clare of HP Labs (above, left) spread Tom Osborne’s ASM (algorithmic state machine) design technique throughout HP and wrote a book on the topic in 1973.


However, a big problem loomed. Dave Maitland had designed the NMOS 4-kbit ROM by himself. The three NMOS II chips that would go into the hybrid microprocessor were too large and complex to be designed by one person. However, no one at HP knew how to parcel out the design work so that several people could work on one chip together. It had not been done before. Maitland and Ed Olander did the only reasonable thing they could think of—they went fishing in the clear Wyoming lakes north of Loveland to discuss the problem in a quiet setting.

And the answer is…

The solution that Olander and Maitland came up with on the lakes in Wyoming was microprogramming, which was first developed by Maurice Wilkes for the EDSAC computer in 1951. Tom Osborne had essentially used it in the HP 9100’s design a few years before, although the hardware controlled by the HP 9100’s rope-memory microcode ROM didn’t really resemble the classical model of a processor. In 1972, microprogramming was hardly a new design technique, but it had not yet been used in IC design.

The advantage of the microcoded-design approach for the hybrid microprocessor is that it divided the design work into two portions: the hardware design of the processor’s functional units and the programming of these functional units to implement the architecture’s machine instructions (control and timing). A small group of engineers could design the functional units and other engineers could create the microcode, which would drive control registers on the chip that caused the functional units to execute the hybrid microprocessor’s instructions. The two design groups could work in tandem, which would save time.

This IC-design technique appears in the groundbreaking book Introduction to VLSI Design, written by Carver Mead and Lynn Conway and published in 1980. The “Mead and Conway” book served as the inspiration and guiding light to thousands of chip designers in the 1980s. The design technique of using a microprogram ROM to control a data path on a chip was first developed at HP in Loveland for the hybrid microprocessor. It is now a bedrock foundation of all chip design.

It won’t all fit

Analysis of the design task at hand by Dave Maitland and HP Loveland’s process-development engineers made it apparent rather quickly that all of the desired features wouldn’t fit on one of the new NMOS chips, unless it was a very big chip. At any given level of process development, IC-fabrication technology can economically make chips only so big. Any bigger and the defect densities on the manufactured chips drive yields to unacceptably low levels. (The larger chips will either get too expensive or impossible to make.)

The early processor architectural analysis clearly indicated that some partitioning of the processor would be needed. All of the logic would not fit on one chip and yet the processor design required minimal signal-path length and capacitance so that the resulting processor design would run at high clock rates to achieve the desired performance. (Disappointing Bill Hewlett, who had been very dissatisfied with the performance of the second-generation desktop calculators, was not an option.)

The processor design quickly turned to hybrid manufacturing techniques to solve the partitioning problem. The processor logic was divided into three NMOS chips: the binary processor chip (BPC), the extended math chip (EMC), and the I/O chip (IOC). These three chips would be attached and wire-bonded to a ceramic substrate that would use printed-circuit traces to interconnect the chips, creating a hybrid device that behaved as one chip.


The BPC implemented 56 instructions that were considered the core HP 211x instructions. It implemented the HP 211x architecture’s two accumulators (A and B), the program counter (P), the return-stack pointer (R), six flags (including four external flags driven by inputs from other chips on the hybrid or system components outside of the hybrid), and the multilevel indirect addressing scheme. The BPC’s instructions included memory-reference, skip, alter, complement, and shift/rotate instructions. The BPC also implemented the new stack pointer required to run code from ROM.

BPC Chip Layout03

BPC chip photo showing the various sections of the processor.
Photo courtesy of Hewlett-Packard Company.

Although the BPC alone lacked the I/O bus, advanced interrupt, and DMA capabilities planned for the hybrid microprocessor, it could reference I/O devices that were mapped into the BPC’s memory space by using memory-reference instructions from its 56-instruction repertoire. The BPC was designed so that it could be used by itself as a 16-bit microprocessor by packaging it in a more conventional ceramic DIP (dual inline package). It was used this way in the HP 9871A impact printer, which was developed by Bob Bump and Gary Paulson (introduced in 1975), the very successful HP 9872A graphics plotter (introduced in 1977), and the revolutionary HP 9874A glass-platen digitizer (introduced in 1978), which was developed by Frank Carau and Larry Brown, the electronic and mechanical engineer respectively. The HP 9871A was the first HP product to use the BPC.

HP 9871A Impact Printer02

The HP 9871A daisy-wheel impact printer, introduced in 1975, was
the first product to incorporate the NMOS II BPC microprocessor.
Photo Courtesy of Hewlett-Packard Company

The IOC implemented 12 new I/O instructions, two stack pointers (C and D), a 2-level vectored-interrupt controller, and the DMA controller. The new I/O instructions looked like the HP 211x minicomputer I/O instructions, which referenced an address space separate from memory. The HP 2116 I/O instructions had used a 6-bit I/O select code to address the 48 I/O slots available in a fully expanded HP 2116 minicomputer. The hybrid microprocessor’s I/O instructions redefined that 6-bit I/O select-code field into a 4-bit select code and a 2-bit register code. This remapping allowed desktop calculators based on the hybrid microprocessor to address as many as 16 peripheral devices (using the 4-bit select code). The 2-bit register code subdivided each peripheral select code into eight addressable 16-bit registers (four writeable control and data registers and four readable status and data registers). This new I/O scheme proved remarkably flexible.

The IOC’s instructions consisted of a DMA group (five instructions), an interrupt group (two instructions), a stack group (six instructions) that used the C and D stack pointers, and an I/O group (two instructions). The IOC’s I/O instructions performed I/O through four “phantom” registers labeled R4 through R7, located in the hybrid microprocessor’s memory-address space at locations 0004 through 0007. A memory-read or -write operation directed at these memory addresses initiated I/O cycles to the specified register in the connected I/O device using the select code stored in the IOC’s peripheral address (PA) register at memory location 0009. (Note: HP generally used octal notation back in the 1970s, but the register addresses used here are hexadecimal, in recognition that octal notation is now thoroughly archaic.)

The IOC employed synchronous I/O cycles—there was no hardware handshaking with the peripheral-device registers. Instead, polled I/O operations read a status register in the peripheral device (this register was always readable) to determine if data was ready (for I/O read operations) or if the peripheral device was idle (for write operations). When the peripheral device was ready, the software would perform the desired data read or write. For interrupt and DMA operations, the peripheral device would only assert the interrupt or DMA request when it was ready for the next transaction, thus effecting a handshake mechanism.

The IOC’s priority-interrupt scheme was based on select code. There were 16 select codes. The upper eight select codes were assigned to the high-priority (level 2) interrupt group and the lower eight select codes belonged to the low-priority (level 1) interrupt group. Each group had its own interrupt line into the processor. When a peripheral device asserted one of the interrupt lines, the IOC performed an interrupt poll to determine the select code of the interrupting device. If more than one device in the priority group was requesting the interrupt, the device with the highest select code within the priority group was granted the interrupt. Level 2 devices could interrupt level-1 interrupt service routines because they had the higher priority level.

The EMC implemented 15 instructions, mostly used for the BCD arithmetic that had become a standard part of HP Loveland’s calculators. These instructions were developed by profiling and analyzing the arithmetic routines used in the HP 9810, 9820, and 9830 to determine which instructions would most speed arithmetic computations. It was therefore quite convenient that the previous generation of desktop calculators had been based on similar processor architecture.

Eleven of the EMC instructions operate on BCD-coded, 3-word (12-digit) mantissa data. A twelfth instruction performed binary 16x16-bit multiplication (using Booth’s algorithm) to produce a 32-bit result. Another instruction cleared the BPC’s decimal-carry register. The remaining two instructions implemented block-move and block-clear operations on data blocks ranging from 1 to 16 words.

The IDA bus

The BPC, EMC, and IOC would connect to each other over an internal 16-bit bus on the hybrid called the IDA (Instruction/Data/Address) bus that time-multiplexed instructions, addresses, and data words. Each of the three chips had its own internal controller, instruction register, and instruction decoder. In effect, the BPC fetched the next instruction for all three chips and each chip would then decode the instruction simultaneously. The chip recognizing the newly decoded instruction as its own would take over control of the IDA bus (and the rest of the processor) for the duration of that instruction. The other chips simply ignored the instruction. After executing the fetched instruction, the BPC would fetch the next instruction and the process would start over again.

Processor Hybrid Block Diagram03

The Hybrid Microprocessor consisted of three NMOS II chips: the BPC, EMC, and IOC.
Four bipolar interface buffers (BIBs) coupled the NMOS chips to the rest of the system.

Image courtesy of the Hewlett-Packard Company.

Because each of the three chips (BPC, EMC, and IOC) contained its own working registers and because the other two chips might need access to the contents of a register in a third chip, all hybrid microprocessor registers were mapped into the first 32 locations in the hybrid microprocessor’s memory space. A bus-request/bus-grant handshake allowed any of the three NMOS chips to acquire control of the IDA bus and then move data across it either to another of the NMOS chips, to memory, or to a peripheral device. The bus-grant signal was daisy-chained and the IOC was first in line on the chain, so it had the highest priority for the IDA bus. (I/O requests sometimes cannot wait.) Through these mechanisms and protocols, the IDA bus moved register data among the three NMOS processor chips and throughout the system.

Designing the chips

With the system partitioned, work turned to designing the actual chips. Bill Eads became the project leader for the BPC and the EMC. Dave Maitland became the project leader for the IOC and the NMOS II 16-kbit ROMs that would hold the operating-system and programming-language code. Maitland eventually took over management of the entire hybrid microprocessor project.

The BPC development team included project leader Bill Eads; engineers Dennis Peery, Ken Eldredge, and Wally Wahlen; and IC-layout specialist Bill Thayer, who had troubleshot circuitry as a technician on the HP 9101 Extended Memory for the HP 9100A desktop calculator.

Armed with just Tom Osborne’s ASM design methodology, the BPC team designed their chip mostly by hand. Commercial EDA tools for chip design and layout simply didn’t exist back then. If the team needed a design tool, they had to create it. For example, Eads recalls that the BPC team ran a single-pass logic simulation of the BPC’s design on an HP 9820 desktop calculator. That was the extent of HP’s chip-design automation in 1972.

Bill Eads moved from HP Santa Clara to Colorado and started working at HP Loveland on April 10, 1972. He worked with Olander and Maitland to define the hybrid microprocessor, formed his BPC design team, and designed the BPC. The the mask patterns were taped out on April 8, 1973 and sent to Santa Clara to make the photomasks. The HP engineers, who had never before designed a microprocessor, managed to design one in 363 days.

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It took two days less than a year to assemble the BPC design team, lay out the chip, and produce
a tape for mask generation. This image is a scan of acetates produced from the actual, original BPC masks.
This version of the chip had a couple of design bugs that were fixed in the next version a few months later.

Image courtesy of Bill Eads

They had functional first-silicon chips in hand a few weeks later but a few things didn’t work right. The compare instruction was supposed to skip the next instruction if a designated value stored in memory (“compare” was a memory-reference instruction) wasn’t equal to the value stored in the designated accumulator (A or B). Instead, the first-silicon BPC skipped if the values were equal. In addition, one instruction group (possibly the shift/rotate group) didn’t decode correctly and therefore didn’t work. However, a few software patches circumvented those flaws and allowed work to progress. A second spin on the silicon produced a fully functional BPC a few months later.

Each of the three NMOS II chips designed for the hybrid microprocessor came out roughly the same size: approximately 4.7mm on a side. Each chip incorporated a microcode ROM containing approximately 8000 bits and, on average, 6000 transistors (2000 equivalent gates) to implement the logic circuits. The chips used four power supplies (5, 7, 12, and -5V) and could run at clock rates exceeding 10 MHz.

There were also four small bipolar ICs on the hybrid microprocessor. Theses chips were called BIBs (bidirectional interface buffers). The 8-bit BIBs provided voltage-level translation between the NMOS BPC, EMC, and IOC chips on the hybrid processor and the bipolar logic in the rest of the calculator system. The BIBs also provided the low-impedance signal-driving ability that was needed to drive the memory and I/O busses throughout the rest of the calculator system, beyond the enclosed world of the hybrid microprocessor. Two BIBs buffered the NMOS processor chips from the memory bus and two more BIBs buffered the I/O bus. Like the NMOS chips, the bipolar BIBs were made in Loveland.
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TThe completed ceramic hybrid microprocessor included the three NMOS II chips
(the three larger, square chips) and four bipolar BIBs (the four small chips above
the three larger NMOS II chips).

Photo courtesy of the Hewlett-Packard Company


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A closeup of the completed ceramic hybrid microprocessor shows the large number of bond wires
required to connect the three NMOS II chips (the three larger, square chips)
and four bipolar BIBs (the four small chips) to the ceramic substrate.

Artifact courtesy of Dyke Shaffer. Photo by Steve Leibson


Rubber baby buggy bumpers

Just getting the chips designed was one problem. Transforming the chips into a manufacturable hybrid was another. The techniques of attaching IC die to a ceramic substrate and bonding out the signals with fine gold wires were well understood—they were the standard techniques every IC manufacturer used to make integrated circuits including Maitland’s 4-kbit NMOS ROMS. However, it wasn’t at all clear how to bridge the hybrid processor’s signals from the ceramic substrate to the circuit board or how to get the waste heat out of the hybrid assembly.

Maitland worked with HP’s materials engineers and purchasing agents to find an interconnect scheme that would allow the hybrid microprocessor to be attached easily to the processor board in a desktop calculator. He wanted a method that was reliable, resistant to the effects of heat and humidity, and that would allow for easy assembly and disassembly in case the processor failed and had to be replaced. Ease of assembly and disassembly ruled out the usual through-hole pins such as those on the ROMs.

Finally, Maitland got the call he needed. One of the materials engineers had found a new type of compression connector that used a thin cylinder of elastomer (think about a long, thin, pink pencil eraser) encased in gold-plated wire rings from one end to the other. By clamping this elastomeric connector between the hybrid substrate and the pc board, signals flowed from pads on the ceramic substrate, through the wire rings, and onto pads located on the processor board. As long as the ceramic substrate and the circuit board were carefully aligned so that their corresponding signal pads lined up, all the connections between the hybrid microprocessor and the circuit board would be made in the one quick assembly operation.

Several critical problems had to be solved to make this interconnect scheme work. The circuit board and ceramic substrate had to be precisely aligned. The assembly mechanism needed to be keyed so that the hybrid microprocessor could not be mounted in the wrong orientation (thus smoking the processor when first powered on). The clamping pressure had to be sufficient to ensure a strong, reliable electrical connection but not so strong as to permanently deform the elastomeric connector, which would make the connection unreliable. The mechanical assembly work had to be simple enough to be performed by production-line workers, not engineers. Finally, the connection had to prove reliable over time despite the effects of heat and humidity.

Maitland recalls getting a lot of pushback from the quality and reliability engineers who sarcastically referred to the elastomeric connectors as “rubber baby buggy bumpers.” They didn’t trust this rather exotic interconnection scheme, for good reason. In any electronic system, connectors are among the least reliable electronic components. They frequently cause frustrating, intermittent failures that are very hard to troubleshoot. Maitland conducted the environmental tests needed to convince everyone that the connection would be reliable. It’s a testament to Maitland’s ingenuity that HP 9825A desktop calculators with these elastomeric rubber baby buggy bumpers are still functioning 30 years later.

The Honda cylinder head

Maitland solved the heat-dissipation, alignment, keying, and clamping-pressure problems with one relatively inexpensive component: a die-cast aluminum heat sink. The heat sink sported a number of cooling fins along the top that made it look like a component removed from an automobile engine. Other engineers kidded Maitland that he was apparently using a Honda cylinder head as a key component in the next-generation desktop calculators.

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The hybrid microprocessor was built on a white ceramic substrate, capped with a metal lid, and then nestled in a cast aluminum heat sink.

Artifact courtesy of Dyke Shaffer. Photo by Steve Leibson.

Bolts mechanically staked to the processor circuit board in an asymmetric pattern aligned with corresponding holes in the heat sink so that the heat sink and the circuit board were aligned. The same pattern of holes was punched into a clear plastic carrier that held the four elastomeric connectors in a rectangular pattern so that the connectors aligned to the heat sink. The hybrid ceramic substrate nestled in a cavity in the heat sink that exactly matched the outline of the ceramic so the hybrid substrate was also aligned to the heat sink and a beveled corner in the ceramic substrate keyed the substrate to the heat sink cavity. Thus the heat sink served to both cool the ceramic substrate assembly and to align it with all of the other assembly components.

When the heat-sink/ceramic-hybrid assembly was bolted to the circuit board, the elastomeric connectors were sandwiched between the ceramic substrate and the circuit board. Assembly took less than a minute, everything fit within tolerances, and the connections were made between the processor and circuit board quickly and reliably. It was a simple, elegant, and relatively cheap solution to a number of complicated engineering problems.

HP 9825 Processor Board Small03

The first product to use the HP 16-bit hybrid microprocessor was the HP 9825A desktop calculator. This is the processor board from an HP 9825. The hybrid microprocessor is on the right under the large, finned aluminum heat sink (dubbed the “Honda cylinder head”). Photo by Steve Leibson.

Various versions of HP’s 16-bit hybrid microprocessor served as the heart of several desktop computers including the HP 9825A/B, HP 9831A, HP 9835A/B, and HP 9845A/B/C. Ed Miller wrote a data book and manual about the hybrid Microprocessor. It was called the “How They Do Dat Manual” and it was illustrated by HP Loveland’s in-house engineer and cartoonist Rand Renfroe. The documentation allowed other HP divisions to use the hybrid microprocessor in their own products.

HP’s Santa Rosa Division used the hybrid microprocessor as the heart of its HP 8566A and 8568A spectrum analyzers. In fact, development of the HP 8566A and 8568A started before the first hybrid processor was made, so the early prototypes of these analyzers used an HP 2100A minicomputer as the control processor. The engineers at HP Santa Rosa, in particular Lynn Wheelright, had a preference for Algol, a structured high-level language that was popular in the 1970s. Wheelright developed a compiler for the hybrid microprocessor as well, an an Algol variant that he dubbed “Wheelgol.” HP owned up to programming the spectrum analyzers in Algol, but kept the name “Wheelgol” under wraps. Later, when the HP 8566A and 8568A spectrum analyzer designs migrated to the Motorola 68000 microprocessor, Wheelright found it very easy to change the compiler’s back end to target the newer microprocessor.

HP’s Colorado Springs Division also used the hybrid microprocessor (minus the EMC) in various incarnations of its HP 64000A Logic Development System, a microprocessor development system and in-circuit emulator used to develop embedded software for a number of different microprocessors including Intel’s 8086, Zilog’s Z80, and Motorola’s MC68000. In all, HP sold products based on HP Loveland’s hybrid microprocessor and its constituent chips (BPC, EMC, and IOC) for more than a decade. Quite a track record for the world’s first 16-bit microprocessor, which very few people had ever heard of, until now.

The How They Do Dat Manual Small02

The How They Do Dat Manual documented the use and operation of the hybrid microprocessor. It was written by Ed Miller and illustrated by Rand Renfroe. Photo by John Keith.

Problems in production

Just because a product or component is released to production doesn't mean there are no more problems with it. Such was the case with the hybrid microprocessor, which had at least three problems after it was released to production. First, there was a serious yield problem with the IOC. Sometimes, an IOC wafer would exit the Loveland IC fab without a single good die on the wafer. This low yield made the IOC chips, in particular, quite dear.

After many months, the IOC yield problem was traced to one incorrectly implemented contact (a single missing rectangle) on one of the IC's mask layers. Because there were essentially no automated design tools back then, the only way to find this sort of implementation error was to search for it by visually by inspecting artwork pen plots.  The missing contact rectangle wasn't discovered for a year after noticing an unusual relationship existed between mask misalignment and yield.  Eventually, the mask defect was found by chance when a process engineer just happened to notice something amiss on a pen plot of a mask layer.

Pen plots were huge multi-color drawings produced to review the IC layouts. Watching these plots being created was a truly memorable experience. A huge machine called a XYnetics flat-bed plotter produced the pen plots. It occupied a special spot in the CAD area. The giant pen plotter consisted of a 2-axis linear stepping motor and a 4-pen head that was magnetically suspended below a linear platen (the linear-motor equivalent of a stator). The pen carriage, which was attached to the linear motor’s forcer (the equivalent of a circular motor’s rotor), moved back and forth over the plotter’s 4x8-foot bed as necessary to mark large sheets of paper stretched across the bed. The unmistakable racket of the XYnetics plotter could be heard day and night as it produced an endless queue of check prints for use as review sheets and release documentation.

Two more problems with the hybrid microprocessor in production were the lack of a good tester for finished devices and a signal glitch that was present in all the hybrids. It fell to a newly hired engineer named Dyke Shaffer to solve these problems.

Shaffer went to engineering school at Cal Poly in his home town of San Luis Obispo in the early 1970s. He mainly studied analog and RF design but he also took an interest in digital design and noted the rise of the microprocessor. In fact, he started to carry a TI TTL (digital IC) data book around and taught himself digital design during an antennas class, while the professor was covering topics that Shaffer had already mastered. Thus he was quite ready to tackle these two hybrid-related problems when he started work at the Calculator Products Division in Loveland.

Dodging the floppy

When Shaffer arrived at HP Loveland in July, 1976, it first looked as though he'd be going into production engineering along with the HP 9885 floppy disk drive. The drive had been designed by Sandy Chumbley, who had started with HP as a technician but grew into the roles of engineer and, eventually, manager. Chumbley had hosted Shaffer during his initial HP interview and was responsible for giving Shaffer his first assignment.

Simply stated, production engineering was not a valued position at HP but Shaffer avoided the HP 9885 production-engineering slot when a member of the HP 9885 development team volunteered for the position. Instead, Shaffer first wrote some much-needed design tools needed to evaluate mask artwork. He wrote these tools in Fortran and they ran on an HP 2115 minicomputer. During his first summer at HP, Shaffer developed software that checked for mask design-rule errors, computed layout capacitance, and extracted a connection net list from a list rectangles stored on punched paper tape.

Shaffer’s next task was to modify the hybrid microprocessor’s ceramic substrate to accommodate a fourth NMOS IC—the AEC (address-extension chip). The AEC was an integrated version of the HP 9845’s address-extension hardware. This integrated version of the address-extension hardware was needed for the smaller HP 9835 desktop computer because the HP 9835’s smaller volume could not accommodate the extra address-extension circuitry as implemented in the HP 9845, which was physically a much larger machine. Two other engineers were already involved in the design of the NMOS II AEC and someone was needed to redesign the ceramic hybrid substrate, which was essentially a single layer of gold interconnect on a 1.7x3-inch ceramic circuit board. Shaffer got the assignment.

After analyzing the elastomeric contact geometry used in the original 82-pin hybrid, Shaffer determined that Maitland’s rubber-baby-bumper connectors could support the smaller pad geometry required to create the additional connections. An initial layout of the new 107-pin substrate was populated with devices and tested through the use of an adapter board that was installed on the existing production tester.

Designing a better tester

On his first visit to the production area, Shaffer found that the hybrid microprocessor tester essentially consisted of an entire HP 9825 desktop calculator with a hole cut in it so that hybrid processors to be tested could be dropped into place. This tester had been built by an engineer named Joe Fucetola. Essentially, the production test for the hybrid microprocessor consisted of clamping the processor in place and seeing if the calculator would power up correctly. If it did, the hybrid processor must be operable. Otherwise it was bad. Unfortunately, this sort of go/no-go test doesn't provide much in the way of diagnostic information, which is required for developing a mature production process. In addition, the physical configuration of the tester prevented the probing of signals on the hybrid microprocessor during the test, further inhibiting failure analysis.

To his amazement, Shaffer found that the adapter board for the 107-pin version of the hybrid microprocessor worked in the existing, makeshift production tester. The hybrid manufacturing group had been using the production HP 9825 with a hole cut in it to accommodate a hinged retainer assembly that held the processor to be tested. Shortening the retainer and adding the adapter board to translate the 82-pin layout used with the original HP 9825 hybrid microprocessor into the proposed 107-pin layout for the HP 9835 version of hybrid microprocessor made testing of the new processor possible.

But the production tester’s original design still prevented probing the assembly during test, so there wasn't much help in evaluating failures. That's when Shaffer discovered that all hybrid microprocessors that failed were simply being set aside, presumably for some future time when their failures could be analyzed so they could be repaired. The existing test situation was clearly not a very effective solution for a production environment. Consequently, Shaffer decided to develop a more practical production tester for the all three versions of the hybrid microprocessor then in production. (The HP 9845 incorporated two different versions of the hybrid microprocessor.)

It took Shaffer several months to wire-wrap his first production tester for the various versions of the hybrid microprocessor. That prototype tester was built on a prototyping board that had been created during the development of the HP 3000 minicomputer. This prototyping board was large—about the right size for the job—and it had some important features needed to accommodate circuitry that worked with the hybrid microprocessor’s 16-bit word width and 6-MHz clock rate (which represented high-speed digital design at the time).

HP used Shaffer's wire-wrapped tester for a year. It broke from time to time, mostly due to the pins-up (dead-bug) orientation of its boards and the extra IC's swimming among those pins. These extra ICs were added from time to time to implement design changes in the tester. However, Shaffer was always on hand to fix things when they broke. During the year that the wire-wrapped version of this tester was in use, Shaffer redesigned the tester using printed-circuit boards to create a more durable tester. This final version of Shaffer's hybrid-microprocessor tester was used for 10 more years until HP finally retired the hybrid microprocessors.

Early in the year 2014, I received this photo from Shaffer:

HybridTester1982 Small1

Dyke Shaffer’s last production testers for the 16-bit HP Hybrid Microprocessor. These testers were used for the last ten years of Hybrid Microprocessor production. Photo by Dyke Shaffer.

Dyke wrote: “This is the only picture I remember taking of the two BPC hybrid testers as they were in production for the last 10 years of the run of bpc hybrids in Fort Collins. It was the culmination of 2 years of work from redesign of the ceramic substrates thru the wire wrap version of the tester to these two fully featured versions with their 14 pcb assemblies and industrial design that I did to facilitate manufacturing test, debug and functional test.”

Follow the bouncing ground

These experiences transformed Shaffer into HP’s resident expert on the operation and testing of the hybrid microprocessor and he next tackled another, intermittently occurring problem with the microprocessor. The problem was a signal glitch that appeared on the hybrid's control signals. This glitch was synchronized to transitions on the processor’s main address/data buses. The cause of the problem turned out to be ground bounce.

As Shaffer discovered, in all electronic systems, ground isn't necessarily ground. There are two uses for system ground in digital systems: as the dc power return and as the ac signal return path. Power ground is a dc return path for the power supply. Signal ground is an ac return path for signals. The ac path is most important when signals are in transition. There are two ways of coupling noise into the signal ground: noise due to shared impedance and noise due to magnetic coupling.

If there is substantial impedance in the ground path, a high-current pulse can actually raise the ground voltage above its desired level of zero volts. If this happens, the resulting noise spike can show up on any control signal that is being asserted low. If the noise spike is large enough, it can upset logic connected to the affected control signals, for instance in memory boards.

This is precisely what was happening to the hybrid microprocessor. One gold trace on the ceramic hybrid served as both the signal and power grounds because the chips themselves combined power and signal grounds into one pad set. As the BIBs (bipolar interface buffers) switched on and off, their integral output buffers dumped high-current spikes into the original hybrid's ground trace, which served both the BIBs and the NMOS II chips. These current spikes caused the ground voltage level to jump half a volt and caused a corresponding voltage jump in all of the hybid microprocessor's internal and external control signals. System circuitry attached to the processor’s external signals could misidentify these spikes as logic-level transitions, which would result in incorrect system operation.

The solution to the ground-bounce problem was to split the ground-return path for the NMOS IC's on the hybrid substrate from the ground-return path for the BIBs that interfaced the hybrid microprocessor’s internal bus to the external memory and I/O buses. Shaffer redesigned the hybrid substrate by splitting the power and signal grounds. Instead of using two processor pins for a single ground, he thinly separated the grounds, assigning each to one of the two ground pins, creating separate power/signal grounds for the BIBs and for the NMOS II chips.

The two grounds now joined only at the circuit board where heavier metal planes presented lower circuit impedances, which greatly reduced the ground bounce at the ground pads of the NMOS II chips. The ground pads on the BIBs spiked even higher than before (from 1V to as much as 1.5V on some of the hybrid microprocessors) but the BIBs contained only inverters, no registers, and therefore the ground-bounce effect was safely limited to the memory and I/O data lines and blocked from reaching and affecting the microprocessor’s critical control signals.


The hybrid microprocessor’s ground-bounce problem was solved by splitting the signal and power grounds at the input pad and routing the two grounds separately to the chips in the hybrid. The split ground appears in this closeup. It’s the fourth pin below the number 41.

Artifact courtesy of Dyke Shaffer. Photo by Steve Leibson.

Split Ground 82-pin hybrid04

As the resident expert on the hybrid microprocessor, Shafffer also expanded his work into software. He wrote a binary program for the HP 9825 that, among other things, implemented an incremental assembler for the hybrid microprocessor’s instruction set and a set of commands to build and access symbol tables, perform arbitrary base conversion between numeric and string variables, and numerous other utility commands that were used during the development and deployment of other electronic tools used during the production lifetime of HP’s 98x5 series of desktop computers. In 1983, Shaffer moved to HP’s Santa Rosa Division in California and finally got back to the analog and RF work that had originally attracted him to electrical engineering. But he never left his digital experiences in Colorado far behind.


The information on this page came from interviews with Bill Eads, Dave Maitland, Ed Olander, and Dyke Shaffer and from the following sources:

Christopher R. Clare, Designing Logic Systems Using State Machines, McGraw-Hill, Inc, 1973.

William D Eads and David S Maitland, “High-Performance NMOS LSI Processor,” HP Journal, June 1976, p 15-18.

William D Eads, Jack M Walden, and Edward L Miller, “A Dual-Processor Desk-Top Computer: The HP 9845A,” Chapter 31, Computer Structures: Principles and Examples, edited by Daniel P Siewiorek, C Gordon Bell, and Allen Newell, McGraw-Hill Book Company, 1982, p 508-532.

Michael S Marzalek and Lynn M Wheelright, “Developing the Digital Control System for the Model 8568A Spectrum Analyzer,” HP Journal, June 1978, p 16-20.

Carver Mead and Lynn Conway, Introduction to VLSI Systems, Addison-Wesley Publishing Company, 1980.

Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana, “Microcode Processing: Positioning and Directions,” IEEE Micro, July-August 2003, p 21-30.

M V Wilkes and J B Stringer, “Microprogramming and the Design of the Control Circuits in an Electronic Digital Computer,” Chapter 11, Computer Structures: Principles and Examples, edited by Daniel P Siewiorek, C Gordon Bell, and Allen Newell, McGraw-Hill Book Company, 1982, p 158-163.

A Pocket Guide to Hewlett-Packard Computers, Hewlett-Packard Company, 1969.



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